Curious by nature.
Building with intent.

AI Accelerator RTL Design Intern

KLE TECHNOLOGICAL UNIVERSITY · TECHXCELERATE 2026 · BELAGAVI

• Designed a 4x4 weight-stationary systolic array (signed INT8 inputs, 32-bit accumulation) in SystemVerilog with parameterized modules for the PE, PE array, weight loader, activation skew, output collector, and control FSM.
• Pipelined multiply-accumulate datapath with diagonal activation skew and FSM-controlled preload, compute, and drain phases; one 4x4 multiply completes in 18 clock cycles (1.5 µs at 12 MHz).
• Implemented on iCE40UP5K (VSDSquadron FPGA Mini) with Yosys and nextpnr at 12 MHz, with a UART interface, power-on reset, and cycle counter; 16 multipliers mapped to LUTs since the array exceeds the 8 DSP blocks.

RISC-V SoC and FPGA IP Development Intern

VLSI SYSTEM DESIGN (VSD) · VIRTUAL

• Designed and integrated 3 memory-mapped peripheral IPs (GPIO, Multi-Register GPIO, PWM) into a custom 32-bit RISC-V SoC in Verilog RTL, with 8+ control, status, and data registers and SoC-level address decoding.
• Achieved timing closure at 20.34 MHz across CPU, memory, UART, GPIO, and PWM subsystems; 1,638 logic cells (31% utilization) and 16 BRAM blocks on iCE40UP5K.
• Debugged bring-up issues (reset sequencing, MMIO errors, memory initialization, pin conflicts) and validated peripherals with C firmware and UART tests.

B.Tech — Electronics & Communication Engineering

St. Martin's Engineering College, Hyderabad · 2023–2027 · CGPA 7.45 / 10.

2nd Place — National VLSI Hackathon (36-hour)

Designed and deployed a Smart Parking Controller on an Artix-7 FPGA; recognized for RTL optimization and implementation quality.

System Design with Verilog — NPTEL

Course by Prof. Shaik Rafi Ahamed of IIT Guwahati. Scored 65%, Elite category.

IEEE CASS Student Chapter Chair

Serving as Chair of the IEEE Circuits and Systems Society (CASS) Student Chapter, supporting student engagement and technical learning around circuits and systems, VLSI, embedded systems, and related areas.